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1 features q 15 to 50mhz shift clock support q 50% duty cycle on receiver output clock q low power consumption q cold sparing all pins q + 1v common mode range (around +1.2v) q narrow bus reduces cable size and cost q up to 1.05 gbps throughput q up to 132 megabytes/sec bandwidth q 325 mv (typ) swing lvds devices for low emi q pll requires no external components q rising edge strobe q radiation-hardened design; total dose irradiation testing to mil-std-883 method 1019 - total-dose: 300 krad(si) and 1 mrad(si) - latchup immune (let > 100 m ev-cm 2 /mg) q packaging options: - 48-lead flatpack q standard microcircuit drawing 5962-01535 - qml q and v compliant part q compatible with tia/eia-644 lvds standard introduction the ut54lvds218 deserializer converts the three lvds data streams back into 21 bits of cmos/ttl data. at a transmit clock frequency of 50mhz, 21 bits of ttl data are transmitted at a rate of 350 mbps per lvds data channel. using a 50 mhz clock, the data throughput is 1.05 gbit/s (132 mbytes/sec). the ut54lvds218 deserializer allows the use of wide, high speed ttl interfaces while reducing overall emi and cable size. all pins have cold spare buffers. these buffers will be high impedance when v dd is tied to v ss . standard products ut54lvds218 deserializer d ata sheet october 2002 l v d s t o - p a r a l l e l t t l pll power down cmos/ttl outputs 21 data (lvds) clock (lvds) receiver clock out figure 1. ut54lvds218 deserializer block diagram
2 pin description notes: 1. these receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. under these conditions receiver inputs will be in a high state. if a clock signal is present, outputs will all be high; if the clock input is also floating/terminated outputs will remain in the last valid state. a floating/terminated clock input will result in a low clock output. figure 2 . ut54lvds218 pinout ut54lvds 218 48 47 46 45 44 43 42 41 v dd 1 rxout 17 2 3 4 5 6 7 8 rxin0- 9 10 11 12 13 14 15 16 gnd n/c lvds gnd lvds v dd lvds gnd rxclk in- 17 18 19 20 21 22 23 24 lvds gnd pll v dd rxclk out rxout0 v dd gnd 40 39 38 37 36 35 34 33 v dd rxout 6 gnd rxout 9 32 31 30 29 28 27 26 25 gnd gnd v dd rxout 18 rxout 19 rxout 20 rxin0+ rxin1- rxin1+ rxin2- rxin2+ rxclk in+ pll gnd pll gnd pwr dwn rxout 16 rxout 15 rxout 14 rxout 13 rxout 12 rxout 11 rxout 10 rxout 8 rxout 7 rxout 3 rxout 5 rxout 4 rxout 2 rxout 1 pin name i/o no. description rxin+ i 3 positive lvds differential data inputs 1 rxin- i 3 negative lvds differential data output 1 rxout o 21 ttl level data outputs rxclk in+ i 1 positive lvds differential clock input rxclk in- i 1 negative lvds differential clock input rxclk out o 1 ttl level clock output. the rising edge acts as data strobe. pin name rxclk out. pwr dwn i 1 ttl level input. when asserted (low input) the receiver outputs are low v dd i 4 power supply pins for ttl outputs and log- ic gnd i 5 ground pins for ttl outputs and logic pll v dd i 1 power supply for pll pll gnd i 2 ground pin for pll lvds v dd i 1 power supply pin for lvds pins lvds gnd i 3 ground pins for lvds inputs txin tx 0 1 2 cmos/ ttl 18 19 20 txclk pcb rxout rx 0 1 2 18 19 20 rxclk pcb shield gnd clock (lvds) data (lvds) lvds cable media dependent figure 3. ut54lvds218 typical application
3 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperature may be increased to +175 c during burn-in and steady-static life. 3. test per mil-std-883, method 1012. 4. for cold spare mode (v dd = v ss ), v i/o may be -0.3v to the maximum recommended operating v dd +0.3v. recommended operating conditions symbol parameter limits v dd dc supply voltage -0. 3 t o 4.0v v i/o voltage on any pin -0. 3 t o (v dd + 0.3v) t stg storage temperature -65 to +150 c p d maximum power dissipation 1 .25 w t j maximum junction temperature 2 +150 c q jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10ma symbol parameter limits v dd positive supply voltage 3.0 to 3.6 v t c case temperature range - 55 to +125 c v in dc input voltage 0v to v dd
4 dc electrical characteristics 1 (v dd = 3.0v to 0.3v ; -55 c < t c < +125 c) notes: 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenc ed to ground. 2. output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not excee d maximum junction temperature specification. 3. guaranteed by characterization. symbol parameter condition min max unit cmos/ttl dc specifications ( pwr dwn , rxout) v ih high-level input voltage 2.0 v dd v v il low-level input voltage gnd 0.8 v v ol low-level output voltage i ol = 2ma 0.3 v v oh high-level output voltage i ol = -0.4ma 2.7 v i ih high-level input current v in =3.6v; v dd = 3.6v -10 +10 m a i il low-level input current v in =0v; v dd = 3.6v -10 +10 m a v cl input clamp voltage i cl = -18ma -1.5 v i cs cold spare leakage current v in =3.6v; v dd = v ss -20 +20 m a i os 2, 3 output short circuit current v out = 0v -15 -130 ma lvds receiver dc specifications (in+, in-) v th 3 differential input high threshold v cm = +1.2v +100 mv v t l 3 differential input low threshold v cm = +1.2v -100 mv v cmr common mode voltage range v id =210mv 0.2 2.00 v i in input current v in = +2.4v, v dd = 3.6v -10 +10 m a v in = 0v, v dd = 3.6v -10 +10 m a i csin cold spare leakage current v in = 3.6v, v dd = v ss -20 +20 m a supply current i cc 3 active supply current cl=8pf (see figure 4) 105 m a i ccpd power down supply current pwr dwn = low, lvds inputs = logic low 2.0 ma
5 receiver switching characteristics 1 (v dd = 3.0v to 3.6v; ta = -55 c to +125 c) notes: 1. receiver skew margin is defined as the valid data sampling region at the receiver inputs. this margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). this margin allows lvds interconnect skew, inte r-symbol interference (both dependent on type/length of cable), and source clock jitter less than 250 ps (calculated from t pos - r pos ) - see figure 11. 2. total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (tccd) and r eceiver (rccd). the total latency for lvds217 serializer and the lvds218 deserializer is (t + tccd) + 2*t + rccd), where t = clock period. 3. guaranteed by characterization. 4. guaranteed by design. symbol parameter min max unit clht 3 cmos/ttl low-to-high transition time (figure 5) 3.5 ns chlt 3 cmos/ttl high-to-low transition time (figure 5) 3.5 ns rspos0 3 receiver input strobe position for bit 0 (figure 10) 0.59 1.33 ns rspos1 3 receiver input strobe position for bit 1 (figure 10) 3.45 4.19 ns rspos2 3 receiver input strobe position for bit 2 (figure 10) 6.30 7.04 ns rspos3 3 receiver input strobe position for bit 3 (figure 10) 9.16 9.90 ns rspos4 3 receiver input strobe position for bit 4 (figure 10) 12.02 12.76 ns rspos5 3 receiver input strobe position for bit 5 (figure 10) 14.88 15.62 ns rspos6 3 receiver input strobe position for bit 6(figure 10) 17.73 18.47 ns rcop 3 rxclk out period (figure 6) 20.00 66.7 ns rcoh 3 rxclk out high time (figure 6) 3.6 ns rcol 3 rxclk out low time (figure 6) 3.6 ns rsrc 4 rxout setup to rxclk out (figure 6) 3.5 ns rhrc 4 rxout hold to rxclk out (figure 6) 3.5 ns rccd 2 rxclk in to rxclk out delay (figure 7) 3.4 8.3 ns rrlls receiver phase lock loop set (figure 8) 10 ms rpdd receiver powerdown delay (figure 9) 2 m s f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz f=50mhz
6 rxclk out odd rx out figure 4. test pattern t even rx out
7 ac timing diagrams 80% clht chlt cmos/ttl output 20% 80% 20% cmos/ttl output 8pf figure 5. ut54lvds218 output load and transition times rcoh rcop rcol rxclk out v dd /2 v dd /2 rsrc rhrc rxout 0:20 figure 6. ut54lvds218 setup/hold and high/low times v dd /2 rxclk in vdiff= 0v rxclk out rccd v dd /2 figure 7. ut54lvds218 clock-to-clock out delay - + v dd /2 v dd /2
8 power down v dd rplls rxclk in rxclk out v dd /2 v dd /2 figure 8. ut54lvds218 phase lock loop set time power down rxclk out rxclkin rpdd v dd /2 figure 9. receiver powerdown delay low v dd /2
9 rxclk in/ differential previous cycle next cycle rxin0 rxin1 rxin2 rspos0 min rspos0 max rspos1 min rspos1 max rspos2 min rspos2 max rspos3 min t clk rspos3 max rspos4 min rspos4 max rspos5 min rspos5 max rspos6 min rspos6 max figure 10. receiver lvds input strobe position
10 rxin+ or rxin- ideal strobe position rxin- or rxin+ c min max min max min max rskm rskm tpposn rsposn tpposn+1 ~1.4v ~1.0v c - setup and hold time (internal data sampling window) defined by rspos (receiver input stroke position min and max tspos - transmitter output pulse position (min and max) rskm > cable skew (type, length) + source clock jitter (cycle to cycle) 1 + isi (inter-symbol interference) 2 cable skew - typically 10 ps-40 ps per foot, media dependent notes: 1. cycle-to-cycle jitter is less than 250 ps at 50mhz. 2. isi is dependent on interconnect length, may be zero. figure 11. receiver lvds skew margin
11 packaging 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance with mil-prf-38535. 4. lead position and colanarity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 7. package dimensions and symbols are similar to mil-std-1835 variation f-19. figure 12. 48-lead flatpack
12 ordering information ut54lvds218 deserializer: ut 54lvds218 - * * * * * device type: ut54lvds218 deserializer access time: not applicable package type: (u) = 48-lead flatpack (dual-in-line) screening: (c) = military temperature range flow (p) = prototype flow lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per utmc manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
13 ut54lvds218 deserializer: smd 5962 - * * * federal stock class designator: no options total dose (r) = 1e5 rad(si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) drawing number: 01535 device type 01 = lvds deserializer class designator: (q) = qml class q (v) = qml class v case outline: (x ) = 48-lead flatpack lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) 01535 ** notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.

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